As is well known, semiconductor memory devices such as MaskROM, EPROM, EEPROM, FLASH, SRAM and DRAM have reached such large density and capacity to store logic information (up to 64 Mbit on a single chip) to require additional circuit portions for managing and synchronizing the different timing activities of the device. For instance, one of these circuit portions is the well known ATD (Address Transition Detection) circuit which is active to synchronize the reading phase of the memory data. The ATD circuit detects each transition on the address or CE terminals or pins of the memory device and generates a synchronization signal which is used for timing many operating functions of the memory device. One of these operating functions is the precharge phase of the memory bit lines which must be charged to a predetermined logic level to allow a good conduction of the memory cell storing the data to be read.
For a EPROM device the bit lines are usually precharged to 1 V, while for a RAM device the bit lines are usually precharged to 5 V. The timing setting provided by the ATD circuit is used also to enable the output data buffer as soon as the sensing amplifier has detected the logic information of the memory cell. Therefore, the detection of an address transition, the sensing of the memory cell and the output presentation of the stored data are all operations which must be synchronized and/or delayed according to the kind and size of the memory device and the technology used. The timing schedule of the memory device must be designed carefully and this design activity can become very hard for the memory device designer.
Prior Art
A known prior art solution is disclosed in the U.S. Pat. No. 5,444,666 assigned to Huyndai. This document discloses a circuit and method allowing the memory device designer to set up the timing schedule of the device. However, this solution has been specifically provided for synchronizing the redundancy circuit portion of the memory device.